A technical response to the debate over industrial policy for semiconductors in Brazil
In a recent column in CartaCapital, Felipe Augusto Machado and James Görgen published "Lessons from the Past", revisiting the 1980s computer market reserve and proposing a set of instruments to recover industrial and technological sovereignty: strategic tariffs, golden shares, stronger state-owned enterprises, and a review of rules that treat firms differently based on where their capital comes from. The thread on X added detailed supporting data on the reserve's performance and its later decline.
I responded publicly on X, and received a careful, well-grounded reply from Machado. The quality of that reply deserved more than a tweet thread, so I am writing here with a bit more room to structure the argument. I write as someone who lives at the intersection of economics and machine learning infrastructure: I hold a degree in economics from the Federal University of Rio de Janeiro (UFRJ) and work as a Senior ML Infrastructure Engineer, so I deal every day with the concrete hardware dependence this debate is trying to address.
To give readers some context, Machado and Görgen's column presents data on the performance of the computer market reserve as evidence of success. In my view, those data are contestable: the comparative literature on liberalization in the computer sector in developing countries, such as Dedrick, Kraemer et al. (2001)[17] comparing Brazil and Mexico, concludes that protecting a domestic computer industry behind barriers was not sustainable in a sector marked by rapid technological change and dominated by multinationals that set global standards. I do not intend to enter that historiographical debate here, however. But the central point is this: even if the reserve's data were entirely correct, the policy proposal that follows from them does not hold up when confronted with the technical structure of the semiconductor chain in 2026.
The disagreement is about the proposed instruments and, more fundamentally, about the technical diagnosis of the chain those instruments are meant to address. The semiconductor chain is not a generic industry that responds to conventional tariff incentives. Each link has barriers of a different kind, and none of them can be solved by trade protection or by the state taking an equity stake. It is worth taking it apart link by link.
The design linkLink to this section
Designing a modern chip is not analogous to writing software. It means defining, in overlapping physical layers measured with nanometer precision, how billions of transistors are organized in silicon to perform a function. This process, known as the RTL-to-GDSII flow[1], begins with a hardware description in a specialized language (Verilog or VHDL) and ends with a binary file containing the full geometric representation of each layer of the chip, ready to be sent to the foundry.
Between the initial concept and that final file sit dozens of interdependent steps, each with its own optimization problems: logic synthesis[2] (translating the RTL description into logic gates, an NP-hard problem that depends on heuristics), floorplanning and placement[3] (defining the physical position of each block and cell on the die while optimizing area, timing, and power consumption), clock tree synthesis[3] (distributing the clock signal with minimal variation across billions of transistors), routing[3] (physically connecting all signals while respecting spacing rules and signal integrity), and timing verification, DRC, and LVS[3] (validating that the physical layout matches the schematic and meets the foundry's speed constraints and manufacturing rules). Every step requires specialized EDA (Electronic Design Automation) tools, in a market that is an oligopoly in its own right[4]: Synopsys (31% of the global market), Cadence (30%), and Siemens EDA (13%) together account for more than 85% of global EDA revenue, according to TrendForce and Griffin Securities.
But the most critical technical barrier is not in the tools. It is in the PDK.
A Process Design Kit[5] is the set of files a foundry provides to its customers so they can design chips for that specific process. A PDK is not generic documentation. It is the proprietary map of how that foundry deposits materials, performs doping, defines layer thicknesses, tolerates process variation, and organizes its design rules. It contains standard cell libraries, transistor models (typically BSIM), physical parameters for each layer, and DRC verification rules[6]. Without it, a design team has no way to guarantee that what it designed will correspond to what gets manufactured. Every foundry has its own, incompatible with the others.
The PDK encapsulates decades of process learning accumulated by the foundry. It is updated frequently, and those updates are synchronized with the EDA tools' license servers[7]. If the designer does not have an active license and an up-to-date PDK, they cannot verify whether the design is compatible with the foundry's current process.
This is where the geopolitical barrier enters. PDKs for advanced nodes are licensed by foundries under NDA and classified by the U.S. Bureau of Industry and Security as export-controlled items under ECCN 3E001 on the Commerce Control List[8]. Any university or company outside the United States that wants to receive a controlled PDK needs an approved Technology Control Plan and, depending on the country, a license from the Department of Commerce. In October 2023, BIS expanded those restrictions to explicitly cover EDA software and design tools for chips below 16/14nm[9], in an effort to prevent companies from sending advanced design files to external foundries.
The relationship between a design team and a foundry, then, is not a market transaction that a domestic tariff can replicate or replace. It is a bilateral technological partnership, governed by U.S. regulation, that requires established trust, an NDA, formal licensing, and an ongoing operational link to the physical process of that specific foundry. No trade-protection instrument creates that link, and no golden share unlocks it.
And the cost of getting to the end of this process is structurally high. According to IBS (International Business Strategies)[10], the total design cost of a 5nm chip reaches US$416 million, with tapeout alone costing between US$40 million and US$50 million, rising to US$100 million at the 2nm node. Those costs do not guarantee success: the first-tapeout failure rate is between 15% and 35%[11], requiring iterations ("spins") that multiply time and capital. There are documented cases in which a single analog IP block required 18 tapeouts over 8 years before it was validated.
The front-end manufacturing linkLink to this section
Here the barrier changes nature. It is not just the equipment, although ASML is the world's only supplier of EUV lithography[12] for nodes below 7nm. The barrier is process knowledge accumulated iteratively across generations, given that manufacturing a chip at an advanced node requires more than 1,000 sequential process steps[13] (deposition, doping, etching, lithography, planarization, inspection), each calibrated through a feedback loop between equipment, real high-volume yield, and the specific physical characteristics of that process. As the manufacturing engineering literature[14] describes, each additional step increases time, cost, and the probability of defect formation that kills the device. That accumulated process knowledge cannot be bought or licensed. It exists only as the result of decades of operating at volume.
That is why even China, with more than US$150 billion in public investment[15] through the Big Fund and local funds since 2014, and explicit national mobilization, still operates today with a gap of at least one full generation relative to TSMC. If massive subsidies and political will were enough, China would already have solved the problem. It has not[16]. That empirical fact says more than any theoretical model of industrial policy.
The back-end and OSAT linkLink to this section
This is the most accessible link in the chain but, before discussing how countries are entering it, it is worth examining what exactly gets manufactured at mature nodes (28nm and above) and why mastering that slice of the chain does not address any real concern about technological sovereignty.
Chips made on mature nodes are used in analog devices, power semiconductors, display drivers, automotive chips, MEMS, RF products, and sensors[24]. They are essential components, but they are industrial commodities with compressed margins. China is aggressively expanding capacity in these nodes: according to TrendForce, China is expected to surpass Taiwan in foundry capacity at mature nodes by 2027[25], and the forecast is that it will hold 31% of global 28nm capacity by then[26]. That expansion, subsidized by the Chinese state, is already generating overcapacity and price pressure[24]: average utilization at mature nodes fell below 80% in 2024, and Hua Hong Semiconductor, China's second-largest foundry, posted a 10.9% gross margin and a net loss in the second quarter of 2025[27]. This is a market moving toward rapid commoditization, not strategic margins.
The chips that actually matter for technological sovereignty run on completely different nodes. AI accelerators such as NVIDIA's GPUs (H100, B200, Blackwell), Google's TPUs (Ironwood), and the custom chips from Microsoft (Maia), Amazon (Trainium), and OpenAI are all manufactured on 7nm, 5nm, or below, exclusively by TSMC[28]. TSMC holds essentially 100% market share in logic semiconductors for AI data centers[29]. Even in military applications, where one might imagine mature nodes would suffice, the reality is more nuanced[30]: legacy systems do in fact use 45nm to 250nm nodes for reasons of reliability and radiation hardness, but emerging AI applications in defense, including autonomous systems, electronic warfare, and real-time data processing, depend on sub-5nm nodes.
In other words: investing in 28nm manufacturing capacity in Brazil does not address the dependency that matters. The chips that would be missing in a real scenario of constraints on national sovereignty, such as AI accelerators, high-performance processors, and advanced 5G communications chips, cannot be manufactured at mature nodes, and the chips that can be manufactured at mature nodes are undergoing accelerated global commoditization driven by China, with margins that do not justify the investment.
That said, India has entered the back-end/OSAT link, and the case deserves attention because the mechanism was the opposite of protectionism. The policy change that enabled those investments was the revision of the Semicon India Programme in December 2022[31], when Modi's cabinet standardized the subsidy at 50% of project cost for any process node (the original scheme ranged from 30% to 50% depending on the node), removed the 45-day window for proposal submissions, and opened the incentive to mature nodes.
The results came quickly. Six months later, Micron announced US$2.75 billion for an ATMP plant in Gujarat[18], with the federal government covering 50% of the cost. Tata entered a joint venture with Taiwan's PSMC for a 28nm fab in Dholera[19], and CG Power formed a three-way partnership with Renesas and Thailand's Stars Microelectronics[19]. In every case, the mechanism was attracting outside capital and an external technology partner through market openness, not tariff barriers.
What matters more: the advanced services sector or a low-margin industry?Link to this section
The market concentration in ARM and NVIDIA, which Machado and Görgen correctly identify, is real. But it is worth understanding what these companies actually do, because that clarifies where the value in the chain sits.
NVIDIA, one of the most valuable companies in the world by market capitalization, does not manufacture a single chip. It is a fabless[22] company: it designs GPUs and AI accelerators and outsources 100% of manufacturing to TSMC. ARM goes further: it does not design chips and manufactures nothing. It licenses an instruction set (ISA) and reference architectures so others can design their own processors. Qualcomm, which licenses ARM's ISA for its Snapdragon processors, is itself fabless and depends on TSMC and Samsung Foundry for all manufacturing[32]. Broadcom, AMD, MediaTek: all fabless, all dependent on Asian foundries.
The pattern is clear: the companies that dominate the semiconductor chain do not own factories. They own IP, architectures, software ecosystems, and contractual relationships with foundries. The value sits in the design layer and in intellectual property, not in owning fabrication capacity. Tariffs and golden shares create none of this because they do not create IP, do not accumulate process knowledge, do not unlock access to geopolitically controlled PDKs, and do not generate the market scale that makes an OSAT internationally viable. More important, they do not attract the external technology partner without which no link in this chain is built today.
It is worth noting that even the countries that decided to invest heavily in domestic semiconductor capacity did not use tariffs to do it. The CHIPS Act[20] mobilizes US$52 billion in direct subsidies and tax incentives, the EU Chips Act[21] mobilizes €43 billion, and the Semicon India Programme[18] offers 50% matching to attract technology partners. In every case, the instrument is direct investment in R&D and infrastructure tied to production commitments and knowledge transfer, not trade protection.
What the debate still needs to answerLink to this section
The question the debate still needs to answer is straightforward: which specific economic instrument addresses which specific barrier, at which link in the chain, with which technology partner, and for which end market?
For the design link, the barrier is access to PDKs, EDA tools, and contractual relationships with foundries. The relevant instruments would be human capital formation, bilateral agreements for technology access, and investment in design houses tied to existing foundries. And this is where, in my reading, Brazil's real opportunity lies.
The fabless model[22] illustrates the point well. The largest semiconductor companies in the world, led by NVIDIA and followed by Qualcomm, Broadcom, AMD, and MediaTek, do not own factories: they design chips and outsource manufacturing to foundries such as TSMC and Samsung. American companies hold about 71% of this market[23], and they do so by competing in architecture, intellectual property, and software ecosystems, not in fabrication capacity. A design house is, at bottom, a high-complexity services company, and its margins reflect that: NVIDIA operates with gross margins above 70%, while mature-node foundries such as Hua Hong struggle to hold 11%.
For the front-end manufacturing link, the barrier is process knowledge accumulated over decades of high-volume operation. A realistic response would involve investment in process R&D in partnership with existing foundries and the training of engineers who can operate within these ecosystems, not an attempt to replicate fabs on national territory through state subsidy.
For the OSAT link, the barrier is lower, but it still requires integration with global supplier and customer chains. The most direct path is to make it easier for international OSATs to operate in the country through a competitive regulatory environment and technology cooperation agreements, as India did in attracting Micron to Gujarat.
This distinction is central to the debate about Brazil. The twenty-first century economy disproportionately rewards knowledge-intensive services, and the country has already shown capability in this type of activity, from the banking automation of the 1980s to today's fintech ecosystem. The debate over economic development in Brazil tends to treat sovereignty as synonymous with installed fabrication capacity, which naturally leads to proposals for tariffs and state-owned enterprises. In the semiconductor chain, however, insisting on semiconductor fabrication capacity as the path to sovereignty means pursuing the chain's lowest-margin link and highest capital barrier, when the layer with the highest value added and lowest capital barrier is precisely design, which is a knowledge-intensive services activity. Training engineers, enabling access to PDKs and EDA tools through agreements with foundries, and creating conditions for design houses to operate in the country with access to global markets would be a strategy more aligned both with Brazil's comparative advantages and with the real structure of the chain.
And I write all this without even getting into the chain of critical inputs behind manufacturing: photoresists are dominated by a handful of Japanese companies (Tokyo Ohka Kogyo, JSR, Shin-Etsu), the lenses and mirrors used in lithography equipment are supplied exclusively by Zeiss, the ultra-pure helium required for deposition and cooling processes is a geologically scarce resource with supply concentrated in a few countries, and the photomasks for advanced nodes are produced by an oligopoly that includes Photronics and Toppan. Each of those links has its own barriers to entry, and none of them responds to tariffs.
In my reading of this chain, tariffs and golden shares do not address the real barriers in any of these links. Machado and Görgen attribute the problems of recent decades to the absence of these policies. I disagree with that diagnosis. Whether these mechanisms work in other sectors is a legitimate debate, and broader than this text can contain, but my goal here is to clarify the complexity and maturity of this sector, as well as the level of international integration required for chip manufacturing. What seems important to me, regardless of how one reads the 1980s and 1990s, is that the proposed instruments do not fit the technical structure of the chain they aim to address. Tariffs on semiconductors and electronics make inputs more expensive for the sectors that depend on them most: the digital services industry, the agribusiness that needs IoT and automation, the financial system that runs on imported chips, Brazil's public health system (SUS), which depends on electronic equipment. Without a technology partner and without addressing the real barriers at each link, the practical effect would be to tax the competitiveness of the sectors Brazil already has.
The semiconductor chain requires instruments as sophisticated as the technology one aims to master. Without that technical granularity, any policy proposal runs the risk of repeating the symmetric error: mobilizing national resources in the wrong direction, again.